SN74LVTH2952DWRE4

SN74LVTH2952DWRE4
Mfr. #:
SN74LVTH2952DWRE4
説明:
Bus Transceivers 20-BIT DUAL BUS TRANSCEIVER
ライフサイクル:
メーカー新製品
データシート:
SN74LVTH2952DWRE4 データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
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ECAD Model:
詳しくは:
SN74LVTH2952DWRE4 詳しくは SN74LVTH2952DWRE4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
バストランシーバー
JBoss:
Y
ロジックファミリ:
74LVTH
入力レベル:
LVTTL
出力レベル:
LVTTL
出力タイプ:
3-State
高レベル出力電流:
- 32 mA
低レベル出力電流:
64 mA
伝播遅延時間:
5.3 ns
供給電圧-最大:
3.6 V
供給電圧-最小:
2.7 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SOIC-24
包装:
リール
関数:
登録トランシーバー
高さ:
2.35 mm
長さ:
15.4 mm
回路数:
8
製品:
BiCMOS
テクノロジー:
BiCMOS
幅:
7.52 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
チャネル数:
8
供給電流-最大:
5 mA
動作供給電圧:
2.7 V to 3.6 V
極性:
非反転
製品タイプ:
バストランシーバー
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
トリガータイプ:
ポジティブエッジ
単位重量:
0.022025 oz
Tags
SN74LVTH2952DWR, SN74LVTH2952DW, SN74LVTH2952D, SN74LVTH29, SN74LVTH2, SN74LVTH, SN74LVT, SN74LV, SN74L, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC BUS TRANSCEIVER DUAL 24SOIC
***eco
OCTAL REG TRANSCEIVER WITH CLOCK ENABLE<AZ
***as Instruments
These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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可用性
ストック:
Available
注文中:
2500
数量を入力してください:
SN74LVTH2952DWRE4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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