SN74LVC841ADWRG4

SN74LVC841ADWRG4
Mfr. #:
SN74LVC841ADWRG4
説明:
Latches 10B Bus Interface DType Latch
ライフサイクル:
メーカー新製品
データシート:
SN74LVC841ADWRG4 データシート
配達:
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ECAD Model:
詳しくは:
SN74LVC841ADWRG4 詳しくは SN74LVC841ADWRG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
ラッチ
JBoss:
Y
回路数:
1 Circuit
ロジックタイプ:
Dタイプラッチ
ロジックファミリ:
LVC
極性:
非反転
静止電流:
10 uA
出力ラインの数:
10 Line
高レベル出力電流:
- 24 mA
低レベル出力電流:
32 mA
伝播遅延時間:
7.5 ns at 2.7 V, 6.7 ns at 3.3 V
供給電圧-最大:
3.6 V
供給電圧-最小:
1.65 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SOIC-24
包装:
リール
関数:
透明
高さ:
2.35 mm
長さ:
15.4 mm
出力タイプ:
3-State
タイプ:
Dタイプ
幅:
7.52 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
チャネル数:
10 Channel
入力行数:
10 Line
動作供給電圧:
1.8 V, 2.5 V, 3.3 V
製品タイプ:
ラッチ
リセットタイプ:
リセットなし
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.021006 oz
Tags
SN74LVC841ADWR, SN74LVC841ADW, SN74LVC841AD, SN74LVC841A, SN74LVC84, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE LATCH SGL 3-ST 24SOIC
***as Instruments
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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可用性
ストック:
Available
注文中:
1500
数量を入力してください:
SN74LVC841ADWRG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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