DC1565A-H

Mfr. #:: DC1565A-H
メーカー:: Analog Devices Inc.
説明:: Data Conversion IC Development Tools LTC2153-12: 12-bit, 310Msps, 1.8V Single
ライフサイクル:: メーカー新製品
データシート:: DC1565A-H データシート
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ECAD Model:
詳しくは:: DC1565A-H 詳しくは DC1565A-H Product Details

製品属性
属性値

メーカー：: アナログ・デバイセズ

製品カテゴリ：: データ変換IC開発ツール

JBoss：: Y

製品：: デモンストレーションボード

タイプ：: ADC

ツールは以下の評価用です：: LTC2153-12

動作供給電圧：: 3 V to 6 V

シリーズ：: LTC2153

ブランド：: アナログ・デバイセズ

製品タイプ：: データ変換IC開発ツール

ファクトリーパックの数量：: 1

サブカテゴリ：: 開発ツール

Tags: DC1565, DC156, DC15, DC1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

DC1565A-H 説明

***va Crawler: LTC2153-12: 12-bit, 310Msps, 1.8V Single ADC, 5MHz-140MHz, DDR LVDS Outputs, req DC1371

***ark: 12Bit Analog To Digital-Adc Evaluation Board, Requires Dc890 & Dc1075; Silicon Manufacturer:linear Technology; Silicon Core Number:ltc2153-12; No. Of Bits:12Bit; Sample Rate:310Msps; Kit Application Type:data Converter Rohs Compliant: Na

***log Devices: The LTC2153-12 is a 310Msps 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 67.6dB SNR and 88dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to undersample high frequencies with good performance. The latency is only five clock cycles. DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.6LSBRMS. The digital outputs are double data rate (DDR) LVDS. The ENC+ and ENC– inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. < Bits LTC2153-12 12 LTC2153-14 14 Applications Communications Cellular Basestations Software Defined Radios Medical Imaging High Definition Video Testing and Measurement Instruments

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