SN74ACT7805-25DLR

Mfr. #:: SN74ACT7805-25DLR
説明:: IC SYNC FIFO MEM 256X18 56-SSOP
ライフサイクル:: メーカー新製品
データシート:: SN74ACT7805-25DLR データシート
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詳しくは:: SN74ACT7805-25DLR 詳しくは SN74ACT7805-25DLR Product Details

製品属性
属性値

メーカー: テキサスインスツルメンツ

製品カテゴリ: ロジック-FIFOメモリ

シリーズ: 74ACT

包装: Digi-ReelR

パッケージ-ケース: 56-BSSOP (0.295", 7.50mm Width)

作動温度: 0°C ~ 70°C

取付タイプ: 表面実装

関数: 同期

電圧供給: 4.5 V ~ 5.5 V

サプライヤー-デバイス-パッケージ: 56-SSOP

メモリー容量: 4.5K (256 x 18)

データレート: 40MHz

アクセス時間: 15ns

電流-供給-最大: 400μA

バス-方向: 一方向

拡張型: 幅

プログラム可能-フラグ-サポート: はい

再送信機能: 番号

FWFT-サポート: 番号

Tags: SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7

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Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT7805-25DLR 評価とレビュー

T***v

Very quickly sent and reached the parcel for 2 weeks

2019-04-05

K***s

received, have not tested but looks right

2019-09-20

SN74ACT7805-25DLR 説明

***et: FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R

***i-Key: IC SYNC FIFO MEM 256X18 56-SSOP

***as Instruments: The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.

Market price

モデル	説明	ストック
SN74ACT7805-25DLR DISTI # 296-4457-2-ND	IC SYNC FIFO MEM 256X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ACT7805-25DLR DISTI # 296-4457-1-ND	IC SYNC FIFO MEM 256X18 56-SSOP RoHS: Compliant Min Qty: 1 Container: Cut Tape (CT)	Limited Supply - Call
SN74ACT7805-25DLR DISTI # 296-4457-6-ND	IC SYNC FIFO MEM 256X18 56-SSOP RoHS: Compliant Min Qty: 1 Container: Digi-Reel®	Limited Supply - Call
SN74ACT7805-25DLR DISTI # 595-SN74ACT780525DLR	FIFO 256 x 18 synchronous FIFO memory RoHS: Compliant	0
SN74ACT7805-25DLR		250

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