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SN74ACT3651-30PQ

SN74ACT3651-30PQ
Mfr. #:
SN74ACT3651-30PQ
説明:
FIFO 2048 x 36 synch FIFO Memory
ライフサイクル:
メーカー新製品
データシート:
SN74ACT3651-30PQ データシート
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ECAD Model:
詳しくは:
SN74ACT3651-30PQ 詳しくは SN74ACT3651-30PQ Product Details
製品属性
属性値
メーカー：
テキサスインスツルメンツ
製品カテゴリ：
FIFO
JBoss：
Y
パッケージ/ケース：
BQFP-132
包装：
チューブ
ブランド：
テキサスインスツルメンツ
取り付けスタイル：
SMD / SMT
感湿性：
はい
製品タイプ：
FIFO
ファクトリーパックの数量：
1
サブカテゴリ：
メモリとデータストレージ
単位重量：
0.162567 oz
Tags
SN74ACT365, SN74ACT36, SN74ACT3, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Depth Bi-Dir 2K x 36 132-Pin BQFP Tray
***i-Key
IC CLOCKED FIFO MEMORY 132-QFP
***ark
FIFO Logic IC; FIFO Function:Synchronous; Access Time, Tacc:15ns; Frequency:33.4MHz; Memory Organization - FIFO:2048 x 36bit; Supply Voltage Range:4.5V to 5.5V; Logic Case Style:BQFP; No. of Pins:132 ;RoHS Compliant: Yes
***as Instruments
The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 2048 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion is also possible in word depth. The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for AF\ and AE\ are programmed from port A or through a serial input. The SN74ACT3651 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)
モデル 説明 ストック 価格
SN74ACT3651-30PQ
DISTI # 296-4419-ND		IC CLOCKED FIFO MEMORY 132-QFP
RoHS: Compliant
Min Qty: 36
Container: Tray		Limited Supply - Call
    SN74ACT3651-30PQ
    DISTI # 595-SN74ACT3651-30PQ    		FIFO 2048 x 36 synch FIFO Memory
    RoHS: Compliant    		0
      SN74ACT3651-30PQBi-Directional FIFO, 2KX36, 15ns, Synchronous, CMOS, PQFP132
      RoHS: Compliant      		3
      • 1000:$25.9900
      • 500:$27.3600
      • 100:$28.4800
      • 25:$29.7000
      • 1:$31.9800
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      		 FIFO 512 x 36 synchronous FIFO memory
      可用性
      ストック:
      Available
      注文中:
      3000
      数量を入力してください:
      SN74ACT3651-30PQの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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