SN65LVDS93BDGGR

SN65LVDS93BDGGR
Mfr. #:
SN65LVDS93BDGGR
説明:
Serializers & Deserializers - Serdes FLATLINK TRANSMITTER AND RECEIVER
ライフサイクル:
メーカー新製品
データシート:
SN65LVDS93BDGGR データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
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ECAD Model:
詳しくは:
SN65LVDS93BDGGR 詳しくは SN65LVDS93BDGGR Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
シリアライザーとデシリアライザー-Serdes
タイプ:
シリアライザー
データレート:
2.38 Gb/s
入力方式:
LVTTL
出力タイプ:
LVDS
入力数:
28 Input
出力数:
4 Output
動作供給電圧:
3.3 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
TSSOP-56
包装:
リール
製品:
Serdesトランスミッター
シリーズ:
SN65LVDS93B
ブランド:
テキサスインスツルメンツ
動作供給電流:
75.1 mA
製品タイプ:
シリアライザーとデシリアライザー-Serdes
ファクトリーパックの数量:
2000
サブカテゴリ:
インターフェイスIC
供給電圧-最大:
3.6 V
供給電圧-最小:
3 V
Tags
SN65LVDS93, SN65LVDS9, SN65LVDS, SN65LVD, SN65LV, SN65L, SN65, SN6
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***AS INSRUMENT
The SN65LVDS93B LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the DS90CR286A and SN65LVDS94.
***AS INSTR
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
***AS INSTRUMENTS INCORPORATED
The SN65LVDS93B device requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.
***XS
The SN65LVDS93B is characterized for operation over ambient air temperatures of –40°C to 85°C.
SN65LVDS93B/SN65LVDS93B-Q1 LVDS SerDes Transmitter
OMO Electronic SN65LVDS93B / SN65LVDS93B-Q1 LVDS SerDes (Serializer/Deserializer) Transmitter contains four 7-bit parallel load serial-out shift registers. The device also has a 7 × clock synthesizer and five low-voltage differential signaling (LVDS) drivers. This is all included in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the DS90CR286A and SN65LVDS94. The SN65LVDS93B-Q1 devices are AEC-Q100 qualified for automotive applications.
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可用性
ストック:
Available
注文中:
5500
数量を入力してください:
SN65LVDS93BDGGRの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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