CDC925DLR

Mfr. #:: CDC925DLR
説明:: IC 133-MHZ CLOCK SYNTH 56-SSOP
ライフサイクル:: メーカー新製品
データシート:: CDC925DLR データシート
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ECAD Model:
詳しくは:: CDC925DLR 詳しくは CDC925DLR Product Details

製品属性
属性値

メーカー: テキサスインスツルメンツ

製品カテゴリ: クロック/タイミング-アプリケーション固有

シリーズ: -

包装: テープ＆リール（TR）代替パッケージ

パッケージ-ケース: 56-BSSOP (0.295", 7.50mm Width)

作動温度: 0°C ~ 85°C

取付タイプ: 表面実装

電圧供給: 2.375 V ~ 3.465 V

サプライヤー-デバイス-パッケージ: 56-SSOP

PLL: はい

主目的: IntelCPUサーバー

入力: 結晶

出力: CMOS

回路数: 1

比率-入力：出力: 1899/12/30 1:24:00

差動入力：出力: いいえ/いいえ

周波数-最大: 133MHz

Tags: CDC925D, CDC925, CDC92, CDC9, CDC

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CDC925DLR 説明

***i-Key: IC 133-MHZ CLOCK SYNTH 56-SSOP

***ark: IC, CLOCK SYNTHESIZER, 133MHZ, SSOP-56; Clock IC Type:Clock Synthesizer / Driver; Frequency:133MHz; No. of Outputs:19; Supply Current:12mA; Supply Voltage Range:3.135V to 3.465V, 2.375V to 2.625V; Digital IC Case Style:SSOP ;RoHS Compliant: Yes

***as Instruments: The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100\. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN\ terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP\ or CPU_STOP\, the outputs operate normally. With a low-level applied to the PCI_STOP\ or CPU_STOP\ terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100\ control input. The PCI bus frequency is fixed to 33MHz. Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.

Market price

モデル	説明	ストック
CDC925DLR DISTI # CDC925DLR-ND	IC 133-MHZ CLOCK SYNTH 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
CDC925DLRG4 DISTI # CDC925DLRG4-ND	IC 133-MHZ CLOCK SYNTH 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
CDC925DLR DISTI # N/A	Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr	0
CDC925DLRG4 DISTI # N/A	Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr	0

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