74ALVCH162268DLRG4

74ALVCH162268DLRG4
Mfr. #:
74ALVCH162268DLRG4
説明:
Universal Bus Functions Triple Buffer/Driver W/Open-Drain Output
ライフサイクル:
メーカー新製品
データシート:
74ALVCH162268DLRG4 データシート
配達:
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ECAD Model:
詳しくは:
74ALVCH162268DLRG4 詳しくは 74ALVCH162268DLRG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
ユニバーサルバス機能
JBoss:
Y
ロジックタイプ:
登録バス交換機
ロジックファミリ:
74AL
回路数:
1
伝播遅延時間:
5.9 ns, 5.4 ns
供給電圧-最大:
3.6 V
供給電圧-最小:
1.65 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SSOP-56
包装:
リール
関数:
登録バス交換機
高さ:
2.59 mm
長さ:
18.41 mm
組織:
12 x 2:1
出力タイプ:
3-State
供給タイプ:
独身
幅:
7.49 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
入力行数:
12
出力ラインの数:
24
高レベル出力電流:
- 24 mA
低レベル出力電流:
24 mA
最大クロック周波数:
0.15 GHz, 0.125 GHz, 0.12 GHz
動作供給電圧:
1.8 V, 2.5 V, 3.3 V
極性:
非反転
製品タイプ:
ユニバーサルバス機能
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.024508 oz
Tags
74ALVCH162268, 74ALVCH16226, 74ALVCH1622, 74ALVCH162, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56
***ark
Universal Bus Function IC; Logic Family:ALVC; Supply Voltage Min:1.65V; Supply Voltage Max:3.6V; Package/Case:56-SSOP; No. of Pins:56; Operating Temperature Range:-40°C to +85°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN)\ inputs are low. The select (SEL)\ line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). These control terminals are registered, so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
モデル 説明 ストック 価格
74ALVCH162268DLRG4
DISTI # 74ALVCH162268DLRG4-ND
IC RGSTRD BUS EXCHANGER 56SSOP
RoHS: Not compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    74ALVCH162268DLRG4
    DISTI # 595-74ALVCH162268DG4
    Universal Bus Functions Triple Buffer/Driver W/Open-Drain Output
    RoHS: Compliant
    0
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      可用性
      ストック:
      Available
      注文中:
      2000
      数量を入力してください:
      74ALVCH162268DLRG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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