TLK6002ZEU

TLK6002ZEU
Mfr. #:
TLK6002ZEU
説明:
Ethernet ICs Dual Ch 0.47-6.25 Gbps Multi-Rate Xcvr
ライフサイクル:
メーカー新製品
データシート:
TLK6002ZEU データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
詳しくは:
TLK6002ZEU 詳しくは TLK6002ZEU Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
イーサネットIC
JBoss:
Y
シリーズ:
TLK6002
製品:
イーサネットトランシーバー
トランシーバーの数:
2 Transceiver
データレート:
6.25 Gb/s
インターフェイスタイプ:
JTAG、シリアル
動作供給電圧:
1 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
BGA-324
包装:
トレイ
ブランド:
テキサスインスツルメンツ
供給電流-最大:
250 mA
開発キット:
TLK6002EVM
感湿性:
はい
製品タイプ:
イーサネットIC
ファクトリーパックの数量:
84
サブカテゴリ:
通信およびネットワーキングIC
供給電圧-最大:
1.05 V
供給電圧-最小:
950 mV
単位重量:
0.061655 oz
Tags
TLK6, TLK
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***XS
The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz).
***ASI
TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers.
***AS INSTRUM
The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps.
***AS USD
TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate.
***as Instr.
The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals.
***ASIN
The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors.
***AS INSTRUMENTS INC
The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes.
***ASI
The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfpp when loss of signal replacement of the receive datapath data is enabled (register bit 6.6).
モデル 説明 ストック 価格
TLK6002ZEU
DISTI # 296-27459-5-ND
IC TXRX 0.47-6.25GBPS DL 324BGA
RoHS: Compliant
Min Qty: 1
Container: Tray
1358In Stock
  • 168:$29.4272
  • 84:$32.9120
  • 10:$34.4610
  • 1:$37.3600
TLK6002ZEU
DISTI # TLK6002ZEU
Dual Transmitter/Receiver 324-Pin BGA - Trays (Alt: TLK6002ZEU)
RoHS: Compliant
Min Qty: 84
Container: Tray
Americas - 0
  • 84:$32.2900
  • 168:$31.4900
  • 336:$30.1900
  • 504:$29.4900
  • 840:$28.9900
TLK6002ZEU
DISTI # TLK6002ZEU
Dual Transmitter/Receiver 324-Pin BGA (Alt: TLK6002ZEU)
RoHS: Compliant
Min Qty: 84
Asia - 0
    TLK6002ZEUDual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver4200
    • 1000:$22.0000
    • 750:$22.0700
    • 500:$24.5900
    • 250:$26.1400
    • 100:$26.3300
    • 25:$29.6200
    • 10:$30.5900
    • 1:$32.7200
    TLK6002ZEU
    DISTI # 595-TLK6002ZEU
    Ethernet ICs Dual Ch 0.47-6.25 Gbps Multi-Rate Xcvr
    RoHS: Compliant
    44
    • 1:$37.3700
    • 5:$35.8200
    • 10:$34.4700
    • 25:$32.9200
    • 100:$29.4300
    • 250:$28.0800
    画像 モデル 説明
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    Modulator / Demodulator 300MHz to 4GHz Quad- rature Modulator
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    Mfr.#: LMK04808BISQE/NOPB

    OMO.#: OMO-LMK04808BISQE-NOPB

    Clock Synthesizer / Jitter Cleaner Lo-Noise Clock Jittr Cleaner Dual Lp PLL
    LMK04808BISQE/NOPB

    Mfr.#: LMK04808BISQE/NOPB

    OMO.#: OMO-LMK04808BISQE-NOPB-TEXAS-INSTRUMENTS

    Clock Synthesizer / Jitter Cleaner Lo-Noise Clock Jittr Cleaner Dual Lp PLL
    TRF3705IRGET

    Mfr.#: TRF3705IRGET

    OMO.#: OMO-TRF3705IRGET-TEXAS-INSTRUMENTS

    Modulator / Demodulator 300MHz to 4GHz Quad- rature Modulato
    可用性
    ストック:
    Available
    注文中:
    4500
    数量を入力してください:
    TLK6002ZEUの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
    参考価格(USD)
    単価
    小計金額
    84
    $32.92
    $2 765.28
    168
    $29.43
    $4 944.24
    252
    $28.08
    $7 076.16
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