SN74LV166APWTG4

SN74LV166APWTG4
Mfr. #:
SN74LV166APWTG4
説明:
Counter Shift Registers Parallel Load 8B Shift Registers
ライフサイクル:
メーカー新製品
データシート:
SN74LV166APWTG4 データシート
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ECAD Model:
詳しくは:
SN74LV166APWTG4 詳しくは SN74LV166APWTG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
カウンターシフトレジスタ
JBoss:
Y
カウントシーケンス:
シリアル/パラレルからシリアル
回路数:
1
ビット数:
8 bit
パッケージ/ケース:
TSSOP-16
ロジックファミリ:
LV
ロジックタイプ:
CMOS
入力行数:
9
伝播遅延時間:
23.3 ns, 18.9 ns, 11.9 ns
供給電圧-最大:
5.5 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
包装:
リール
関数:
シフトレジスタ
幅:
4.4 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
出力ラインの数:
1
動作供給電圧:
2.5 V, 3.3 V, 5 V
製品タイプ:
カウンターシフトレジスタ
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.002169 oz
Tags
SN74LV166AP, SN74LV166, SN74LV16, SN74LV1, SN74LV, SN74L, SN74, SN7
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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SHIFT REGISTER SGL 8B 16TSSOP
***ark
Register Logic IC; Logic Family:LV-A; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-40°C to +85°C; Input Type:LVTTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation. The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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ブランドニューオリジナル
可用性
ストック:
Available
注文中:
1500
数量を入力してください:
SN74LV166APWTG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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