SN74GTLP1395PWR

SN74GTLP1395PWR
Mfr. #:
SN74GTLP1395PWR
説明:
Translation - Voltage Levels 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate
ライフサイクル:
メーカー新製品
データシート:
SN74GTLP1395PWR データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
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ECAD Model:
詳しくは:
SN74GTLP1395PWR 詳しくは SN74GTLP1395PWR Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
翻訳-電圧レベル
JBoss:
Y
伝播遅延時間:
9.7 ns
供給電圧-最大:
3.45 V
供給電圧-最小:
3.15 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
TSSOP-20
包装:
リール
特徴:
Partial power down (Ioff), Over-voltage tolerant inputs, Power up 3 state, Bias Vcc, Variable outpu
動作温度範囲:
- 40 C to + 85 C
シリーズ:
SN74GTLP1395
ブランド:
テキサスインスツルメンツ
ロジックファミリ:
GTLP
動作供給電流:
20 mA
製品タイプ:
翻訳-電圧レベル
ファクトリーパックの数量:
2000
サブカテゴリ:
ロジックIC
単位重量:
0.002716 oz
Tags
SN74GTLP1395P, SN74GTLP1395, SN74GTLP1, SN74GTLP, SN74G, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    D***v
    D***v
    KZ

    The goods went long, ordered before the chinese new year, turned out today. The seller honestly warned that he will send the goods only after the holidays. By number, everything came smoothly. How i use in practice i will write about the result. The capacitors themselves are tiny for low boots.

    2019-04-09
    L***a
    L***a
    RU

    Sent quite other details.

    2019-03-17
    L***v
    L***v
    RU

    Ok!

    2019-04-08
*** Stop Electro
Bus Transceiver, GTLP Series, 2-Func, 1-Bit, Configurable Output, CMOS, PDSO20
***as Instruments
Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40 to 85
***ical
Bus XCVR Single 2-CH 3-ST 20-Pin TSSOP T/R
***ource
IC TRNSLTR BIDIRECTIONAL 20TSSOP
***estock Electronics HK limited
IC BUS XCVR LVTTL-GTLP 20-TSSOP
***or
SN74GTLP1395 TWO 1-BIT LVTTL/GTL
***AS INSRUMENT
The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 .
***XS
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.
***AS INS
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.
***AS INSTRUMEN
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.
***AS INSTRUM
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
***XS
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.
***AS INTRUMENTS
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
モデル 説明 ストック 価格
SN74GTLP1395PWR
DISTI # 26643969
Bus XCVR Single 2-CH 3-ST 20-Pin TSSOP T/R
RoHS: Compliant
10000
  • 2000:$1.9658
SN74GTLP1395PWR
DISTI # 296-12467-1-ND
IC TRNSLTR BIDIRECTIONAL 20TSSOP
RoHS: Compliant
Min Qty: 1
Container: Cut Tape (CT)
2017In Stock
  • 1000:$2.2394
  • 500:$2.6553
  • 100:$3.1192
  • 10:$3.8070
  • 1:$4.2400
SN74GTLP1395PWR
DISTI # 296-12467-6-ND
IC TRNSLTR BIDIRECTIONAL 20TSSOP
RoHS: Compliant
Min Qty: 1
Container: Digi-Reel®
2017In Stock
  • 1000:$2.2394
  • 500:$2.6553
  • 100:$3.1192
  • 10:$3.8070
  • 1:$4.2400
SN74GTLP1395PWR
DISTI # 296-12467-2-ND
IC TRNSLTR BIDIRECTIONAL 20TSSOP
RoHS: Compliant
Min Qty: 2000
Container: Tape & Reel (TR)
Temporarily Out of Stock
  • 2000:$2.0655
SN74GTLP1395PWR
DISTI # SN74GTLP1395PWR
Bus XCVR Single 2-CH 3-ST 20-Pin TSSOP T/R (Alt: SN74GTLP1395PWR)
RoHS: Compliant
Min Qty: 2000
Container: Tape and Reel
Europe - 0
  • 2000:€2.5900
  • 4000:€2.2900
  • 8000:€1.9900
  • 12000:€1.8900
  • 20000:€1.7900
SN74GTLP1395PWR
DISTI # SN74GTLP1395PWR
Bus XCVR Single 2-CH 3-ST 20-Pin TSSOP T/R - Tape and Reel (Alt: SN74GTLP1395PWR)
RoHS: Compliant
Min Qty: 2000
Container: Reel
Americas - 0
  • 2000:$2.1900
  • 4000:$2.0900
  • 8000:$1.9900
  • 12000:$1.9900
  • 20000:$1.8900
SN74GTLP1395PWRTwo 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity6000
  • 1000:$1.7700
  • 750:$1.8500
  • 500:$2.1900
  • 250:$2.5800
  • 100:$2.7500
  • 25:$3.1400
  • 10:$3.3700
  • 1:$3.7400
SN74GTLP1395PWRBus Transceiver, GTLP Series, 2-Func, 1-Bit, Configurable Output, CMOS, PDSO20
RoHS: Compliant
19933
  • 1000:$2.0400
  • 500:$2.1500
  • 100:$2.2400
  • 25:$2.3300
  • 1:$2.5100
SN74GTLP1395PWR
DISTI # 595-SN74GTLP1395PWR
Translation - Voltage Levels 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate
RoHS: Compliant
1972
  • 1:$4.1100
  • 10:$3.7000
  • 100:$3.0200
  • 250:$2.8400
  • 500:$2.5700
  • 1000:$2.1700
  • 2000:$2.0600
  • 4000:$1.9800
SN74GTLP1395PW
DISTI # 595-SN74GTLP1395PW
Translation - Voltage Levels 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate
RoHS: Compliant
0
  • 140:$3.6300
  • 280:$3.4100
  • 560:$3.0900
  • 1050:$2.6100
  • 2520:$2.4800
SN74GTLP1395PWG4
DISTI # 595-SN74GTLP1395PWG4
Translation - Voltage Levels Two 1B LVTTL GTLP Adj Edg RateBus Xcvr
RoHS: Compliant
0
    SN74GTLP1395PWRG4
    DISTI # 595-74GTLP1395PWRG4
    Translation - Voltage Levels Two 1B LVTTL GTLP Adj Edg RateBus Xcvr
    RoHS: Compliant
    0
      SN74GTLP1395PWRE4
      DISTI # 595-SN74GTLP1395PWRE
      Translation - Voltage Levels Quad Bus Buffer Gate With 3-State Outputs
      RoHS: Compliant
      0
        SN74GTLP1395PWR 1799
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          可用性
          ストック:
          Available
          注文中:
          1984
          数量を入力してください:
          SN74GTLP1395PWRの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
          参考価格(USD)
          単価
          小計金額
          1
          $4.11
          $4.11
          10
          $3.70
          $37.00
          100
          $3.02
          $302.00
          250
          $2.84
          $710.00
          500
          $2.57
          $1 285.00
          1000
          $2.17
          $2 170.00
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