SN74ACT7807-40PAG

Mfr. #:: SN74ACT7807-40PAG
説明:: FIFO 2048 x 9 synchronous FIFO memory
ライフサイクル:: メーカー新製品
データシート:: SN74ACT7807-40PAG データシート
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詳しくは:: SN74ACT7807-40PAG 詳しくは SN74ACT7807-40PAG Product Details

製品属性
属性値

メーカー：: テキサスインスツルメンツ

製品カテゴリ：: FIFO

JBoss：: Y

パッケージ/ケース：: TQFP-64

包装：: チューブ

ブランド：: テキサスインスツルメンツ

取り付けスタイル：: SMD / SMT

感湿性：: はい

動作供給電圧：: 4.5 V to 5.5 V

製品タイプ：: FIFO

ファクトリーパックの数量：: 1

サブカテゴリ：: メモリとデータストレージ

単位重量：: 0.012720 oz

Tags: SN74ACT7807, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT7807-40PAG 説明

***et: FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 64-Pin TQFP Tray

***i-Key: IC SYNC FIFO MEM 2048X9 64-TQFP

***as Instruments: The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0C to 70C.

Market price

モデル	説明	ストック	価格
SN74ACT7807-40PAG DISTI # 296-4467-ND	IC SYNC FIFO MEM 2048X9 64-TQFP RoHS: Compliant Min Qty: 160 Container: Tray	Limited Supply - Call
SN74ACT7807-40PAG DISTI # 595-SN74ACT780740PAG	FIFO 2048 x 9 synchronous FIFO memory RoHS: Compliant	0
SN74ACT7807-40PAG	FIFO, 2KX9, 25ns, Synchronous, CMOS, PQFP64 RoHS: Compliant	1428	1000:$12.1300 500:$12.7700 100:$13.3000 25:$13.8700 1:$14.9300

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