SN74LV374ADGVR

SN74LV374ADGVR
Mfr. #:
SN74LV374ADGVR
説明:
Flip Flops Octal Edge-Trig D-Ty F-F W/3-State Otpt
ライフサイクル:
メーカー新製品
データシート:
SN74LV374ADGVR データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
詳しくは:
SN74LV374ADGVR 詳しくは SN74LV374ADGVR Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
ビーチサンダル
JBoss:
Y
回路数:
8
ロジックファミリ:
74LV
ロジックタイプ:
Dタイプフリップフロップ
極性:
非反転
入力方式:
シングルエンド
出力タイプ:
シングルエンド
伝播遅延時間:
19.3 ns
高レベル出力電流:
- 16 mA
低レベル出力電流:
16 mA
供給電圧-最小:
2 V
供給電圧-最大:
5.5 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
TVSOP-20
包装:
リール
関数:
Dタイプバスインターフェース
高さ:
1.05 mm
長さ:
5 mm
静止電流:
20 uA
幅:
4.4 mm
ブランド:
テキサスインスツルメンツ
チャネル数:
8
入力行数:
2
出力ラインの数:
1
動作供給電圧:
2 V to 5.5 V
製品タイプ:
ビーチサンダル
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.002123 oz
Tags
SN74LV374AD, SN74LV374A, SN74LV374, SN74LV37, SN74LV3, SN74LV, SN74L, SN74, SN7
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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20TVSOP
***ark
Flip-Flop Logic IC; Flip Flop Type:D; Trigger Type:Positive Edge; Output Type:Tri-State Non-Inverted; Supply Voltage Range:2V to 5.5V; Logic Case Style:TVSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C ;RoHS Compliant: Yes
***as Instruments
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
画像 モデル 説明
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ブランドニューオリジナル
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可用性
ストック:
Available
注文中:
4500
数量を入力してください:
SN74LV374ADGVRの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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