74ALVCH16600DLG4

74ALVCH16600DLG4
Mfr. #:
74ALVCH16600DLG4
説明:
Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
ライフサイクル:
メーカー新製品
データシート:
74ALVCH16600DLG4 データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
詳しくは:
74ALVCH16600DLG4 詳しくは 74ALVCH16600DLG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
バストランシーバー
JBoss:
Y
ロジックファミリ:
74AL
入力レベル:
LVTTL
出力レベル:
LVTTL
出力タイプ:
3-State
高レベル出力電流:
- 24 mA
低レベル出力電流:
24 mA
伝播遅延時間:
6.8 ns
供給電圧-最大:
3.6 V
供給電圧-最小:
1.65 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SSOP-56
包装:
チューブ
関数:
ユニバーサルバストランシーバー
高さ:
2.59 mm
長さ:
18.41 mm
回路数:
1
製品:
CMOS
テクノロジー:
CMOS
幅:
7.49 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
チャネル数:
18
供給電流-最大:
40 uA
動作供給電圧:
1.65 V to 3.6 V
極性:
非反転
製品タイプ:
バストランシーバー
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
トリガータイプ:
ネガティブエッジ
単位重量:
0.024508 oz
Tags
74ALVCH16600D, 74ALVCH16600, 74ALVCH1660, 74ALVCH166, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56
***i-Key
IC UNIV BUS TXRX 18BIT 56SSOP
***eco
18-BIT UBT W/CLK ENABLE
***el Nordic
Contact for details
***as Instruments
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16600 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA\, and CLKENBA\. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
モデル 説明 ストック 価格
74ALVCH16600DLG4
DISTI # 74ALVCH16600DLG4-ND
IC UNIV BUS TXRX 18BIT 56SSOP
RoHS: Compliant
Min Qty: 120
Container: Tube
Limited Supply - Call
    74ALVCH16600DLG4
    DISTI # 595-74ALVCH16600DLG4
    Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
    RoHS: Compliant
    0
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      可用性
      ストック:
      Available
      注文中:
      5500
      数量を入力してください:
      74ALVCH16600DLG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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