74LVCH16652ADLRG4

74LVCH16652ADLRG4
Mfr. #:
74LVCH16652ADLRG4
説明:
Bus Transceivers 16-Bit Bus Trcvr/Reg W/3-St Otpt
ライフサイクル:
メーカー新製品
データシート:
74LVCH16652ADLRG4 データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
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ECAD Model:
詳しくは:
74LVCH16652ADLRG4 詳しくは 74LVCH16652ADLRG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
バストランシーバー
JBoss:
Y
ロジックファミリ:
74LVCH
入力レベル:
LVTTL
出力レベル:
LVTTL
出力タイプ:
3-State
高レベル出力電流:
- 24 mA
低レベル出力電流:
24 mA
伝播遅延時間:
7.3 ns
供給電圧-最大:
3.6 V
供給電圧-最小:
1.65 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SSOP-56
包装:
リール
関数:
バストランシーバー/レジスター
高さ:
2.59 mm
長さ:
18.41 mm
回路数:
2
製品:
CMOS
テクノロジー:
CMOS
幅:
7.49 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
チャネル数:
16
供給電流-最大:
20 uA
動作供給電圧:
1.65 V to 3.6 V
極性:
非反転
製品タイプ:
バストランシーバー
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
トリガータイプ:
ポジティブエッジ
単位重量:
0.024508 oz
Tags
74LVCH166, 74LVCH16, 74LVCH1, 74LVCH, 74LVC, 74LV, 74L
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***eco
16BIT REGISTERED TRANSCEIVER W/ 3-ST<AZ
***i-Key
IC BUS TRANSCVR 16BIT 56SSOP
***as Instruments
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16652A consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Complementary output-enable (OEAB and OEBA\) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVCH16652A. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.
モデル 説明 ストック 価格
74LVCH16652ADLRG4
DISTI # 74LVCH16652ADLRG4-ND
IC TXRX NON-INVERT 3.6V 56SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    74LVCH16652ADLRG4
    DISTI # 595-74LVCH16652ADLRG
    Bus Transceivers 16-Bit Bus Trcvr/Reg W/3-St Otpt
    RoHS: Compliant
    0
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      可用性
      ストック:
      Available
      注文中:
      3000
      数量を入力してください:
      74LVCH16652ADLRG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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