SN74ACT3651-30PCB

Mfr. #:: SN74ACT3651-30PCB
説明:: FIFO 2048 x 36 synch FIFO Memory
ライフサイクル:: メーカー新製品
データシート:: SN74ACT3651-30PCB データシート
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詳しくは:: SN74ACT3651-30PCB 詳しくは SN74ACT3651-30PCB Product Details

製品属性
属性値

メーカー：: テキサスインスツルメンツ

製品カテゴリ：: FIFO

JBoss：: Y

パッケージ/ケース：: HLQFP-120

包装：: チューブ

ブランド：: テキサスインスツルメンツ

取り付けスタイル：: SMD / SMT

感湿性：: はい

製品タイプ：: FIFO

ファクトリーパックの数量：: 1

サブカテゴリ：: メモリとデータストレージ

Tags: SN74ACT365, SN74ACT36, SN74ACT3, SN74ACT, SN74AC, SN74A, SN74, SN7

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT3651-30PCB 説明

***et: FIFO Mem Sync Dual Depth Bi-Dir 2K x 36 120-Pin HLQFP EP Tray

***i-Key: IC CLOCKED FIFO MEMORY 120HLQFP

***ark: FIFO Logic IC; FIFO Function:Synchronous; Access Time, Tacc:15ns; Frequency:33.4MHz; Memory Organization - FIFO:2048 x 36bit; Supply Voltage Range:4.5V to 5.5V; Logic Case Style:HLQFP; No. of Pins:120 ;RoHS Compliant: Yes

***as Instruments: The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 2048 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion is also possible in word depth. The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for AF\ and AE\ are programmed from port A or through a serial input. The SN74ACT3651 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)

Market price

モデル	説明	ストック	価格
SN74ACT3651-30PCB DISTI # 296-4418-ND	IC CLOCKED FIFO MEMORY 120HLQFP RoHS: Compliant Min Qty: 90 Container: Tray	Limited Supply - Call
SN74ACT3651-30PCB DISTI # 595-SN74ACT365130PCB	FIFO 2048 x 36 synch FIFO Memory RoHS: Compliant	0
SN74ACT3651-30PCB	Bi-Directional FIFO, 2KX36, 15ns, Synchronous, CMOS, PQFP120 RoHS: Compliant	49	1000:$13.0000 500:$13.6800 100:$14.2500 25:$14.8600 1:$16.0000

画像	モデル	説明
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	Mfr.#: SN74ACT374DW OMO.#: OMO-SN74ACT374DW-TEXAS-INSTRUMENTS	Flip Flops Tri-State Octal
	Mfr.#: SN74ACT373DBR OMO.#: OMO-SN74ACT373DBR-TEXAS-INSTRUMENTS	Latches Tri-St Octal D-Type

SN74ACT3651-30PCB

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes