MC100LVEL39DWG

Mfr. #:: MC100LVEL39DWG
メーカー:: ON Semiconductor
説明:: Clock Generators & Support Products 3.3V ECL Clock Generator
ライフサイクル:: メーカー新製品
データシート:: MC100LVEL39DWG データシート
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HTML Datasheet:: MC100LVEL39DWG Datasheet MC100LVEL39DWG Datasheet (P4-P6)
ECAD Model:

製品属性
属性値

メーカー：: オン・セミコンダクター

製品カテゴリ：: クロックジェネレータとサポート製品

JBoss：: Y

最低動作温度：: - 40 C

最高作動温度：: + 85 C

取り付けスタイル：: SMD / SMT

パッケージ/ケース：: SOIC-20 Wide

包装：: チューブ

ブランド：: オン・セミコンダクター

製品タイプ：: クロックジェネレータ

ファクトリーパックの数量：: 38

サブカテゴリ：: クロック＆タイマーIC

単位重量：: 0.028254 oz

Tags: MC100LVEL39, MC100LVEL3, MC100LVEL, MC100L, MC100, MC10, MC1

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We provide 90-360 days warranty.

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

MC100LVEL39DWG 説明

***ser: Amplifiers- Audio 3.3V ECL Clock Generator

***i-Key: IC CLOCK GEN ECL 2/4 4/6 20SOIC

***th Star Micro: The MC100LVEL39 is a low skew 2/4 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. In addition by using the VBB output a sinusoidal source can be AC coupled into the device. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock therefore all associated specification limits are referenced to the negative edge of the clock input. Upon startup the internal flip-flops will attain a random state; therefore for systems which utilize multiple LVEL39s the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39 the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.

Market price

モデル	メーカー	説明	ストック	価格
MC100LVEL39DWG DISTI # MC100LVEL39DWGOS-ND	ON Semiconductor	IC CLOCK GEN ECL 2/4 4/6 20SOIC RoHS: Compliant Min Qty: 38 Container: Tube	Limited Supply - Call
MC100LVEL39DWG DISTI # 863-MC100LVEL39DWG	ON Semiconductor	Clock Generators & Support Products 3.3V ECL Clock Generator RoHS: Compliant	0
MC100LVEL39DWG	ON Semiconductor	Low Skew Clock Driver, 100LVEL Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20 RoHS: Compliant	305	1000:$4.2200 500:$4.4500 100:$4.6300 25:$4.8300 1:$5.2000

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