TMS32C5517AZCHA20R

TMS32C5517AZCHA20R
Mfr. #:
TMS32C5517AZCHA20R
説明:
Digital Signal Processors & Controllers - DSP, DSC TMS320C5517 low-power digital signal processor 196-NFBGA -40 to 85
ライフサイクル:
メーカー新製品
データシート:
TMS32C5517AZCHA20R データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
詳しくは:
TMS32C5517AZCHA20R 詳しくは TMS32C5517AZCHA20R Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
デジタルシグナルプロセッサおよびコントローラ-DSP、DSC
JBoss:
Y
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
NFBGA-196
シリーズ:
TMS320C5517
製品:
DSP
芯:
C55x
最大クロック周波数:
75 MHz
データRAMサイズ:
64 kB, 256 kB
動作供給電圧:
1.05 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
ブランド:
テキサスインスツルメンツ
データROMサイズ:
128 kB
インターフェイスタイプ:
I2C, SPI, UART, USB
データバス幅:
8 bit, 16 bit
I / O電圧:
1.8 V, 2.75 V, 3.3 V
命令タイプ:
固定小数点
感湿性:
はい
製品タイプ:
DSP-デジタルシグナルプロセッサおよびコントローラ
ファクトリーパックの数量:
1000
サブカテゴリ:
組み込みプロセッサおよびコントローラ
供給電圧-最大:
1.15 V
供給電圧-最小:
0.998 V
ウォッチドッグタイマー:
ウォッチドッグタイマー
Tags
TMS32C5, TMS32C, TMS32, TMS3, TMS
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***
This device is a member of TI's C5000 fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.
***TEXAS
The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
***XS
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
***AS INSTR
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
***
The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.
***AS INSTR
Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface
***AS INSTR
The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).
***NS
Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
***AS INSTRU
The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).
***NS
The device is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
TMS320C5517 Fixed-Point Digital Signal Processor
OMO Electronic TMS320C5517 Fixed-Point Digital Signal Processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses and two 16-bit data write buses. The device also has additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
Processors
OMO Electronic Processors provide a comprehensive portfolio, proven software, and worldwide support enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.
画像 モデル 説明
TMS32C5517AZCHA20R

Mfr.#: TMS32C5517AZCHA20R

OMO.#: OMO-TMS32C5517AZCHA20R

Digital Signal Processors & Controllers - DSP, DSC TMS320C5517 low-power digital signal processor 196-NFBGA -40 to 85
可用性
ストック:
Available
注文中:
1984
数量を入力してください:
TMS32C5517AZCHA20Rの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
参考価格(USD)
単価
小計金額
1
$10.73
$10.73
10
$9.87
$98.70
25
$9.36
$234.00
100
$8.34
$834.00
250
$7.93
$1 982.50
500
$7.42
$3 710.00
1000
$6.81
$6 810.00
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